1. Field of the Invention
This invention relates to a semiconductor memory device and a test method thereof and, for example, to a semiconductor memory having stacked gate including charge accumulation layer and control gate.
2. Description of the Related Art
Conventionally, a NOR flash memory is known as an electrically data rewritable nonvolatile semiconductor memory. In the NOR flash memory, a drain stress test is made before shipment in order to attain the high reliability of the operation thereof. The drain stress test is to apply voltage to the drain of the memory cell and check whether a leakage of charges occurs or not.
Conventionally, a method of applying program voltage at the drain stress test time to a bit line by use of the same path as that used at the normal program time in order to make the drain stress test is proposed in Jpn. Pat. Appln. KOKAI Publication No. 2005-310303, for example. However, with the configuration disclosed in the above Publication, there occurs a problem that the potential of a bit line is lowered if a failure in which another bit line is shorted to ground potential occurs, for example. The reason is that the conductive resistance of the column gate is low.